1. Field of the Invention
The present invention relates to a modulator used in an analogue-digital converter and a digital-analogue converter and, more particularly, to a delta-sigma modulator (or noise shaper) having resolution over 18 bits.
2. Description of the Related Art
In general, a delta-sigma modulator, which is used in the oversampling an analogue-to-digital converter (hereinafter, referred to as an ADC) and a digital-to-analogue converter (hereinafter, referred to as a DAC) are used as a low-pass filter with respect to input signal, and also the transition of quantized noise is achieved in a high frequency region. With the increase of the order in its architecture and the oversampling ratio, the noise may decrease in frequency band of interest. In particular, since the signal-to-noise ratio is over 100 dB, in the case of the audio signal processing, the modulator is designed at the oversampling ratio of 128 and the order of 4. However, its area may increase. Accordingly, in the case of the audio signal processing of 18-bit resolution, the modulator is typically designed at the oversampling ratio of 64 and a fifth order architecture.
FIG. 1 is a detailed block diagram illustrating a conventional delta-sigma modulator in the fifth order architecture. The conventional delta-sigma modulator, shown in FIG. 1, is described in U.S. Pat. No. 5,274,375. entitled "Delta-Sigma Modulator For an Analogue-to-Digital Converter with Low Thermal Noise Performance", assigned to Crystal Semiconductor Corporation. In FIG. 1, the reference numerals 40, 44, 46, 50 and 52 denote integrators, 54 and 56 multipliers indicating feedback coefficients, 60, 62, 64, 66 and 68 feedforward coefficient blocks, 26 and 28 comparators, 70 a three-level DAC, 38, 42, 48 and 58 summing junctions, respectively.
As shown in FIG. 1, two feedback loops (multipliers 54 and 56) are provided to secure stability of the delta-sigma modulator. In the first feedback loop, the output of the integrator 46 is fed to the summing junction 42 in the front of the integrator 44 via the multiplier 54 having the feedback coefficient of 0.0115. In the second feedback loop, the output from the integrator 52 is fed to the summing junction 48 in the front of the integrator 44 via the multiplier 56 having the feedback coefficient of 0.020. In the delta-sigma modulator including the feedback loops, the more the number of feedback loops is, the higher its stability is. The increase of the feedback loops may cause its linearity to deteriorate.
Particularly, the decrease of the linearity and the increase of its size result from the first feedback loop. Accordingly, it is desired that the coefficient within the first feedback loop is set to a low value in order that the "zero" point in the input signal band can be in close vicinity to the frequency of 0. However, in this case, the low value of coefficient causes the chip size to be increased.